1. Field of the Invention
Embodiments of the invention relate to power semiconductor devices that include a trench gates.
2. Related Art
With a reduction in the power consumption of a power conversion device, it is expected that the power consumption of a power semiconductor device (switching device) which plays a central role in the power conversion device will be reduced. In recent years, a power insulated gate (MOS) semiconductor device with a trench gate structure capable of considerably increasing channel density has been put to practical use as a semiconductor device capable of contributing to reducing the power consumption. An example of the power MOS semiconductor device with the trench gate structure is an IGBT (insulated gate bipolar transistor) which is typified by a power MOSFET (insulated gate field effect transistor).
The bipolar semiconductor device, such as an IGBT, has a structure for preventing the holes injected from a collector from moving to an emitter electrode, that is, a structure for reducing the area ratio of an emitter region which is electrically connected to the emitter electrode, in addition to the trench gate structure for improving channel density. In other words, the bipolar semiconductor device has a structure for relatively increasing the area of a floating region which is formed in the same plane as the emitter region and is disposed at a different position from the emitter electrode so as to be insulated from the emitter electrode. This structure makes it possible to obtain the effect of storing carriers to the emitter of a drift layer. Therefore, it is possible to reduce an on voltage and steady loss even in the layer structure of a general high breakdown voltage semiconductor device in which the on voltage is likely to increase due to a thick drift layer.
The structure of the trench gate IGBT will be described with reference to FIGS. 3 and 4. FIG. 3 is a cross-sectional view illustrating the structure of a main portion of the trench gate IGBT according to the related art. FIG. 4 is a plan view illustrating the structure of the main portion of the trench gate IGBT according to the related art. FIG. 4 is a plan view illustrating a main portion of a region including (a portion of) an active region 30 and (a portion of) an edge termination structure region 40 which is provided in the periphery of the active region 30. FIG. 3 is a cross-sectional view taken along the line B-B′ of FIG. 4. In the main portion plan view illustrated in FIG. 4, for ease of understanding of a surface structure pattern, an aluminum electrode on the outermost surface and a silicon oxide film below the aluminum electrode are not illustrated.
As illustrated in FIGS. 3 and 4, particularly in a region which serves as a main current path in the active region 30, a p base layer 2 (p channel layer) and an n+ emitter region 8 are provided in the front surface of a semiconductor substrate which will be an n− drift layer 1 (n− base layer). In addition, trenches 3 are formed at a depth more than that of the p base layer 2 from the surfaces of the p base layer 2 and the n+ emitter region 8. A plurality of trenches 3 are formed along the surface of the n− drift layer 1 (the surface close to the front surface of the semiconductor substrate), with a predetermined gap a therebetween. A doped polysilicon gate electrode 11 is provided in the trench 3, with a gate oxide film 10 interposed therebetween, to form a trench gate.
An interlayer insulating film 4 is formed on the surface of the n− drift layer 1 so as to cover an upper portion (exposed portion) of the doped polysilicon gate electrode 11 in the trench 3. In addition, a metal film which will be an emitter electrode 5 is formed on the surface of the n− drift layer 1 with the interlayer insulating film 4 interposed therebetween. The metal film which will be the emitter electrode 5 is also formed on the surfaces of the n+ emitter region 8 and the p base layer 2 so as to commonly contact the surfaces. A p+ collector layer 13 is formed on a surface layer of the rear surface of the semiconductor substrate which will be the n− drift layer 1 (n− base layer). A collector electrode 6 comes into ohmic contact with the surface of the p+ collector layer 13.
In many cases, in the trench gate IGBT, a p+ contact layer 9 is provided in the p base layer 2 in order to increase latch-up resistance. It is preferable that an n+ buffer layer 14 be provided between the n− drift layer 1 and the p+ collector layer 13, in order to reduce the thickness of the high-resistance n− drift layer 1. A p-type extension region C which extends from the p base layer 2 to the edge termination structure region 40 is provided in the outer circumference of the active region 30. The trench 3 is not provided in the p-type extension region C.
A region in which a doped polysilicon gate electrode 11 for a gate runner is formed on the surface of the p-type extension region C with the gate oxide film 10 interposed therebetween and an emitter electrode contact hole 21, which is an opening of an oxide film for bringing the emitter electrode 5 into direct contact with a silicon surface, are provided in the surface (the surface close to the front surface of the semiconductor substrate) of the p-type extension region C. The doped polysilicon gate electrode 11 for a gate runner and the doped polysilicon gate electrode 11 for the trench gate structure described above are formed at the same time.
The doped polysilicon gate electrode 11 for a gate runner and the doped polysilicon gate electrode 11 for a trench gate are electrically connected to each other in a portion (not illustrated). An aluminum gate electrode line 12 which will be a gate runner contacts the surface of the doped polysilicon gate electrode 11 for a gate runner through the opening provided in the oxide film. The doped polysilicon gate electrode 11 for a trench gate structure is drawn to the surface of the chip by the aluminum gate electrode line 12.
The edge termination structure region 40 is provided outside the p-type extension region C which is disposed in the outer circumferential edge of the p base layer 2. In the edge termination structure region 40, annular p+ guard rings 15 and 16 are provided at a depth equal to or more than the depth of the p base layer 2, with a predetermined gap from the p-type extension region C. The p+ guard rings 15 and 16 which are a portion of the edge termination structure region 40 surround the active region 30.
Doped polysilicon field plates 18 and 19 are respectively provided on the surfaces of the p+ guard rings 15 and 16, with an insulating film 17 which is formed at the same time as the gate oxide film 10 interposed therebetween. The doped polysilicon field plates 18 and 19 are formed so as to cover the surfaces of the p+ guard rings 15 and 16 and the surface of portions of the n− drift layer 1 adjacent to the p+ guard rings. The p+ guard rings 15 and 16 and the doped polysilicon field plates 18 and 19 are electrically connected to each other in a portion (not illustrated) by an aluminum field plate 20.
For the trench gate IGBT, a structure has been proposed in which an additional trench for reducing the electric field when a depletion layer is spread from the pn junction between the p base layer and the n− drift layer in an off state is provided in a p base layer (corresponding to the p-type extension region C in FIG. 3) which is arranged outside the trench at the outermost (hereinafter, referred to as an outermost trench) in the active region. See, for example, Japanese Patent Application Publication No. JP 10-70271 A (also referred to herein as “Patent Document 1”) and Japanese Patent Application Publication No. JP 2008-103683 A (also referred to herein as “Patent Document 2”).
In addition, as another trench gate IGBT, a structure has been proposed in which an isolation trench is formed outside a termination trench among trench gates in an active region, a p base layer of the active region extends to the isolation trench, and an emitter electrode which is connected to the surface of the active region is also connected to the surface of the end of the extended p base layer. See, for example, Japanese Patent Application Publication No. JP 2006-5248 A (also referred to herein as “Patent Document 3”).
However, in the trench gate IGBT according to the related art disclosed in Patent Document 3, when the depletion layer is spread from the pn junction between the p base layer and the n− drift layer in the off state, the curvature radius of the depletion layer is likely to be reduce at the bottom of the trench in the active region. This phenomenon is noticeable particularly at the bottom of the outermost trench (termination trench) in the active region. Therefore, the electric field at the bottom of the termination trench is likely to be higher than that at the bottom of the trench other than the trench at the termination of the active region. As a result, the electric field is likely to concentrate on the bottom of the termination trench and avalanche breakdown occurs at a low voltage, which results in a reduction in the breakdown voltage. In the actual design of an element structure, a high-resistivity semiconductor substrate is used to increase the thickness of the n− drift layer, considering a reduction in the breakdown voltage due to the concentration of the electric field on the bottom of the termination trench. As a result, for example, the on voltage and turn-off loss increase.
As disclosed in Patent Document 1 and Patent Document 2, in the structure in which only the gap between the additional trenches provided outside the termination trenches is reduced in order to reduce the electric field formed at the bottom of the additional trench, the necessary electric field reduction effect is not obtained. In addition, as disclosed in Patent Document 3, in the structure in which the p base layer and the emitter electrode are connected to each other on the surface of the chip-outer-circumferential-side end of the p base layer which extends from the active region to the outside of the termination trench, holes are likely to be emitted from a connection portion of the p base layer with the emitter electrode when the device is turned off. Therefore, there is a concern that the electric field will concentrate on the connection portion and breakdown will occur due to current concentration.
Thus, as described above, there exists certain problems in the related art